A BiCMOS circuit family for a 0.45 μm CMOS/BiCMOS sea of gates

Author

Boudon, Gerard ; Plassat, Dominique ; Cullet, Rene ; Trauet, Robert ; Mauchauffee, Daniel

Author_Institution

IBM France, Corbeil-Essonnes, France

fYear

1991

fDate

12-15 May 1991

Abstract

A BiCMOS standard cell circuit library is mixed in an existing 300 K-CMOS ASIC (application-specific integrated circuit) sea of gates featuring 0.45-μm L_eff FETs. The 3.6-V BiCMOS circuits with a 15-GHz NPN are compatible in voltage levels with the CMOS. Various terminator/level shifter BiCMOS circuits permit performance from 180 ps to 220 ps. A Booth/Wallace tree 16×16 multiplier and an array of 2700 AND-ORs for a noise experiment have been implemented on a 86 K, 6.7-mm chip

Keywords

BIMOS integrated circuits; CMOS integrated circuits; VLSI; application specific integrated circuits; logic arrays; multiplying circuits; 0.45 micron; 15 GHz; 16 bit; 180 to 220 ps; 3.6 V; 6.7 mm; AND-OR arrays; ASIC; BiCMOS circuit family; Booth Wallace tree multiplier; CMOS; application-specific integrated circuit; gate arrays; level shifters; noise experiment; sea of gates; standard cell circuit library; BiCMOS integrated circuits; CMOS process; CMOS technology; FETs; Feedback circuits; Inverters; Latches; Libraries; Threshold voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164106

Filename

164106