System-level design for FPGAs

Summary form only given. The complexity of FPGAs has progressed to the point where they are likely to become the dominant platform for the majority of system on chip (SoC) design starts within the foreseeable future. Many of the system-level challenges that we first encountered with ASIC SoCs are fast becoming relevant for high end FPGAs. Functional verification and debug in particular are emerging as two of the biggest concerns. In this talk, we review the traditional and emerging approaches to system-level design used with ASIC designs and evaluate their appropriateness in the context of FPGAs. We proceed to explore how FPGA technology might present new opportunities to offset the system-level design challenges. Finally, we look at some novel approaches to the problem that exploit the unique features of FPGAs.