Cost-efficiency code generation approach of software pipelining for FPGA architectures

Software pipelining is an optimization algorithm, which is unrolling iteration to improve the executive efficiency by loop-unrolled technology. As the loop is unrolled by more times, we will get large bigger codes that we need the hardware resource sharply increased. To solve the problem which needs large hardware resource because of unrolling the loop, we propose a new approach which is reconstructing state to share state resource and establishing the finite state machine model of software pipelining. It is the cost-efficiency code generation approach of software pipelining. The model can fulfill to reuse hardware resource and need less hardware resource by using the FSM to control the reusing of kernel codes of the pipelining technology.