DocumentCode :
2090678
Title :
Modeling a reconfigurable system for computing the FFT in place via rewriting-logic
Author :
Ayala-Rincón, Mauricio ; Nogueira, Rodrigo B. ; Llanos, Carlos H. ; Jacobi, Ricardo P. ; Hartenstein, Reiner W.
fYear :
2003
fDate :
8-11 Sept. 2003
Firstpage :
205
Lastpage :
210
Abstract :
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the fast Fourier transform (FFT) using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.
Keywords :
fast Fourier transforms; logic design; reconfigurable architectures; rewriting systems; FFT computation; design abstraction level; design space exploration; dynamically reconfigurable architectures; fast Fourier transform; reconfigurable computing; reconfigurable system modeling; rewriting theory; rewriting-logic; Application specific integrated circuits; Brazil Council; Circuit simulation; Computational modeling; Computer architecture; Costs; Field programmable gate arrays; Hardware; Reconfigurable architectures; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on
Print_ISBN :
0-7695-2009-X
Type :
conf
DOI :
10.1109/SBCCI.2003.1232830
Filename :
1232830
Link To Document :
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