Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

Author

Tanaka, T. ; Suzuki, K. ; Horie, H. ; Sugii, T.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

1994

fDate

7-9 June 1994

Firstpage

11

Lastpage

12

Abstract

Using direct bonded SOI wafers just 40 nm thick, we fabricated p/sup +/-n/sup +/ double-gate SOI MOSFETs. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. For Lg=0.19 /spl mu/m, we obtained an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V. These are the fastest reported values for this gate length. The high performance is attributed to the large drain current, the low series resistance, and the reduction of the parasitic drain junction capacitance.<>

Keywords

CMOS integrated circuits; insulated gate field effect transistors; semiconductor-insulator boundaries; silicon; 0.19 micron; 27 to 43 ps; SOI MOSFETs; Si-SiO/sub 2/; direct bonded SOI wafers; drain current; p/sup +/-n/sup +/ double-gate; parasitic drain junction capacitance; series resistance; short-channel behavior; ultrafast low-power operation; Capacitance; Delay effects; Electrodes; Inverters; Laboratories; MOS devices; MOSFETs; Ring oscillators; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324402

Filename

324402