Title :
An ultra-low power 0.1 /spl mu/m CMOS
Author :
Mii, Y. ; Wind, S. ; Taur, Y. ; Lii, Y. ; Klaus, D. ; Bucchignano, J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Ultra-low power operation of 0.1 /spl mu/m CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are carried out in a power supply-threshold voltage design space. Experimental results show a ring oscillator delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor=0.01) at 0.4 V. A 20X reduction in power/circuit is achieved at the same performance level as 0.25 /spl mu/m CMOS.<>
Keywords :
CMOS integrated circuits; VLSI; digital integrated circuits; integrated circuit technology; integrated logic circuits; 0.1 micron; 0.4 to 1 V; CMOS IC; active power; gate delay; ring oscillator delay; standby power; ultra-low power operation; CMOS technology; Circuits; Degradation; Emergency power supplies; Inverters; Microelectronics; Power supplies; Propagation delay; Ring oscillators; Threshold voltage;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324403
