State assignment of controllers for optimal area implementation

The state assignment of controllers presented aims at preparing further minimizations of the next-state and output logic implementation on standard cells. This is done by detecting situations in the control flowgraph leading to these further minimizations, deducing constraints on the state assignment and finding a solution on the hypercube satisfying them. The originality of this paper is to propose situations minimizing both the gate area and the wiring area. For this purpose, full collapsing product term constraints are defined and are respected first. In a second step, constraints leading to factorizations are respected as long as they do not prevent the previous factorizations. Results on global area decrease are given on controller benchmarks