Applied factory physics study on semiconductor assembly and test manufacturing

Cycle time is an important indicator for measuring able performance. Sometimes, we may need to lower the WIP level to reduce cycle time; however, too much WIP reduction may lead to unexpected station starvation. We extend the principles of factory physics, and develop a methodology called O_L graph, which integrates Little´s Law and the operation curve to quantify the interdependency among operations factors like OEE, cycle time, throughput, WIP level, etc.. The methodology has been implemented at Intel Shanghai to set the baseline for chipset assembly and test factory operations and to help us identify opportunities for improvement. A cycle time and WIP level reduction of 10% has been achieved