A modular memory and process verification vehicle for a sub-micron BiCMOS telecom technology

Author

Schultz, Kenneth J. ; Gibson, G. F Randall ; Phillips, Richard S. ; Silburt, Allan L. ; Gibbins, Robert G. ; Mehta, Nayan

Author_Institution

Bell-Northern Res. Ltd., Ottawa, Ont., Canada

fYear

1991

fDate

12-15 May 1991

Abstract

A verification vehicle was implemented in parallel with process development to accelerate memory and product introduction. 320 Kb of SRAM, DRAM, and ROM were integrated using architectural and circuit techniques supporting rapid analysis of manufacturability and characterization of memory-specific parasitics. It is shown that the BIST (built-in self-test) circuitry is well-suited to providing vital information on manufacturing defects and yield in minimal test time. The novel parasitic characterization circuitry permits measurements which serve to greatly improve the simulation accuracy of the final memory designs, allowing product deployment to take place less than one year after initial test chip access

Keywords

BIMOS integrated circuits; application specific integrated circuits; built-in self test; integrated circuit technology; integrated circuit testing; 320 kbit; BIST; BiCMOS telecom technology; DRAM; ROM; SRAM; built-in self-test; manufacturing defects; memory-specific parasitics; modular memory; parasitic characterization circuitry; process verification; telecom ASICs; yield; Acceleration; Automatic testing; Built-in self-test; Circuit testing; Integrated circuit manufacture; Integrated circuit yield; Manufacturing processes; Random access memory; Read only memory; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164133

Filename

164133