Title :
Optimization of salicide processes for sub 0.1-/spl mu/m CMOS devices
Author :
Goto, K. ; Yamazaki, T. ; Fushida, A. ; Inagaki, S. ; Yagi, H.
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
Abstract :
In scaled CMOS devices with gate less than 0.1 /spl mu/m long, the reduced gate resistance obtained using salicide is a key issue for high-speed performance Recently, many studies have examined salicide processes for short gates. A low gate resistance with gates less than 0.1 /spl mu/m long has not been reproducibly obtained, however, because of agglomeration. We studied the disadvantages of the conventional Ti, Pt and Co salicide for 0.1-/spl mu/m CMOS devices. We developed an improved Co salicide process which fabricated devices at gates less than 0.1-/spl mu/m long with a low gate resistance and good electrical properties.<>
Keywords :
CMOS integrated circuits; VLSI; cobalt compounds; integrated circuit technology; metallisation; 0.1 micron; Co salicide process; CoSi/sub 2/; electrical properties; gate resistance; scaled CMOS devices; sub 0.1-/spl mu/m CMOS devices; Annealing; CMOS process; Contact resistance; Etching; Human computer interaction; Kelvin; Leakage current; Paper technology; Silicides; Tin;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324428
