Transmission gate delay models for circuit optimization

Accurate macromodels for CMOS transmission gates are presented. Signal delay, area consumption and power dissipation are determined by a few technology dependent parameters. Different transistor widths, input waveforms and varying loading conditions are considered. The calculated delay times of CMOS circuits including transmission gates differ only 10 percent when compared with SPICE results. The presented macromodels can be incorporated into the CAD tool MOGLO for automatic transistor sizing in CMOS logic circuits. MOGLO determines optimal tradeoff solutions for CMOS circuitry at low computational cost taking into account conflicting criteria such as delay, area and power.<>