DocumentCode :
2092266
Title :
A yield enhancement methodology for launching new technologies
Author :
Huang, Jiu ; Franca, Daniel
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
fYear :
2005
fDate :
13-15 Sept. 2005
Firstpage :
491
Lastpage :
494
Abstract :
A traditional Pareto chart can be misleading if an overall yield is low. The traditional reject Pareto chart weights heavily for rejects at the front end of line. In order to address the shortcoming, we introduce a new final yield impact Pareto chart, which provides us with much accurate yield loss information to identify yield improvement projects. Furthermore, when we prioritize and allocate the resources for yield improvement projects, we must also consider some other important constraints. A matrix similar to a FMEA matrix is introduced to consider all constraints for prioritizing yield improvement projects.
Keywords :
Pareto analysis; failure analysis; integrated circuit yield; quality control; FMEA matrix; failure mode and effect analysis; final yield impact Pareto chart; reject Pareto chart; yield enhancement methodology; yield improvement projects; yield loss information; Automobiles; Chemical industry; Chemical technology; Design optimization; Investments; Job shop scheduling; Medical services; Problem-solving; Resource management; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on
Print_ISBN :
0-7803-9143-8
Type :
conf
DOI :
10.1109/ISSM.2005.1513414
Filename :
1513414
Link To Document :
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