A new algorithm for transistor sizing in CMOS circuits

This paper describes a new algorithm for automatic transistor sizing in CMOS circuits. The algorithm consists of three phases: critical path analysis, transistor sizing and transistor desizing. This approach is different from conventional sizing methods that optimize a given design locally, using one or several paths at a time. The authors´ algorithm reduces the delays of all paths in a given design simultaneously. Using their transistor desizing approach, the minimal transistor areas can be achieved to meet a set of timing requirements. Furthermore, by tuning NFET and PFET transistor sizes separately, this algorithm has control over rise and fall time delays of a gate depending on the input trigger signal. Experimental results show that this algorithm can improve the delay in approximately linear time