Layout extraction and verification methodology for CMOS I/O circuits

This paper presents a layout extraction and verification methodology which targets reliability-driven I/O design for MOS VLSI chip, specifically to guard against electrostatic discharge (ESD) stress and latchup. We propose a new device extraction approach to identify devices commonly used in CMOS I/O circuits including MOS transistors, field transistors, diffusion and well resistors, diodes and silicon controlled rectifiers (SCRs) etc. Unlike other extractors, our extractor identifies circuit-level netlist based on the specified ESD stress condition. In addition, novel techniques are proposed for the identification of parasitic bipolar junction transistors (BJTs).