Integrally accurate resolver-to-digital converter (RDC)

In a resolver signal processing system, sine and cosine signals processed by the resolver-to-digital converter (RDC) obtained from a resolver is looped back as the resolver´s sine wave excitation signal as to ensure that the signal is in-phase and frequency with generated output signals. Regenerating constant-amplitude sine wave is a challenge since output signal amplitude grows and decays over time based on its initial signal. In this work, an approach is proposed to digitally generate sinusoidal signal based on a state machine. Progression of states in a state machine that is fixed enables maintaining constant amplitude signal. Implementation using Altera FPGA Cyclone II (EP2C8Q208C8) shows sinusoidal signal is produced with less hardware resources for higher angle and data resolution compared to the popular method of ROM-based lookup table.