DocumentCode
2095563
Title
What´s between simulation and formal verification?
Author
Dill, David L.
Author_Institution
Stanford Univ., CA, USA
fYear
1998
fDate
19-19 June 1998
Firstpage
328
Lastpage
329
Abstract
This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.
Keywords
formal verification; logic testing; functional test coverage; large designs; simulation; verification techniques; Algorithm design and analysis; Analytical models; Computational modeling; Delay effects; Emulation; Formal verification; Humans; Permission; Testing; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724491
Link To Document