A CMOS Low-Noise, Low-Dropout Regulator

This paper presents a design technique of low noise fully CMOS low-dropout voltage regulator based on suitable error amplifier and unity feedback network. The inherent thermal and flicker noise are represented by equivalent current and voltage sources. The small-signal transmission performance of noise is analyzed to find out the main noise contribution sources and the methods to minimize them. The proposed LDO is processed in a standard 0.35 um CMOS process. With the proposed techniques, the LDO regulator features output noise performance of 9 pV/¿Hz at 100 HZ, PSRR of 86 dB, line regulation rate of 0.1 mV/V, load regulation rate of 0.001 mV/mA, and response time less than 2 us with a 1 uf output capacitor.