Simulation of surface engineering for ultra shallow junction formation of PMOS for the 90nm CMOS technology node and beyond

Author

Bonnouvrier, Jérôme ; Lenoble, Damien ; Robilliart, Etienne ; Schwartzmann, Thierry ; Jaouen, Hervé

Author_Institution

Central R&D, STMicroelectronics, Crolles, France

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

155

Lastpage

158

Abstract

Since the junctions in the most advanced CMOS devices are thinner and thinner, the influence of the surface of silicon is thus becoming significant on dopant diffusion. In this paper, based on experimental data, a methodology for calibration is proposed, taking this effect of surface into account. SIMS profiles are accurately fitted by simulation using a simple model of recombination of interstitials; the phenomenon of POED is well reproduced and validated by TCAD ID simulations. Then, the impact of POED on the PMOS performances is quantified by anticipation with 2D TCAD simulations.

Keywords

CMOS integrated circuits; calibration; diffusion; elemental semiconductors; interstitials; secondary ion mass spectra; semiconductor process modelling; silicon; surface treatment; technology CAD (electronics); 2D TCAD simulations; 90 nm; CMOS technology node; PMOS; SIMS profiles; Si; TCAD 1D simulations; calibration; dopant diffusion; interstitials; recombination; silicon; surface engineering; ultra shallow junction formation; Annealing; Boron; CMOS technology; Calibration; Oxidation; Research and development; Semiconductor device modeling; Semiconductor process modeling; Silicon; Surface engineering;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233660

Filename

1233660