DocumentCode :
2097719
Title :
Scalable one chip design for a multiplex tap with timestamping [QoS validation applications]
Author :
Burda, Ralf ; Folgmann, Manfred ; Kolodziejczyk-Strunck, Klaus
Author_Institution :
Fac. of Electr. Eng., Dortmund Univ., Germany
fYear :
2004
fDate :
16-18 Nov. 2004
Firstpage :
776
Lastpage :
777
Abstract :
Precise tracking of delay, delay jitter and packet loss is one of the key issues in validating quality of service (QoS) goals in practice. As VoIP is deployed, low cost solutions are needed to enable a good coverage of hot spots even in the networks of medium sized or small enterprises. This work reports on the development and integration of an appropriate capturing tool in a one chip core.
Keywords :
Internet telephony; internetworking; multiplexing equipment; network analysis; network interfaces; quality of service; synchronisation; telecommunication traffic recording; timing jitter; IWP; QoS validation; VoIP; delay jitter tracking; interworking point; multiplex tap; network interfaces; network traffic capturing tool; one chip core capturing tool; packet loss tracking; scalable capturing tool; timestamping; Chip scale packaging; Clocks; Costs; Databases; Delay estimation; Hardware; Jitter; Local area networks; Quality of service; Semiconductor device measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Local Computer Networks, 2004. 29th Annual IEEE International Conference on
ISSN :
0742-1303
Print_ISBN :
0-7695-2260-2
Type :
conf
DOI :
10.1109/LCN.2004.106
Filename :
1367322
Link To Document :
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