• DocumentCode
    2102208
  • Title

    Triple Rail Logic Robustness against DPA

  • Author

    Lomne, Victor ; Ordas, Thomas ; Maurine, Philippe ; Torres, Lionel ; Robert, Michel ; Soares, Rafael ; Calazans, Ney

  • Author_Institution
    LIRMM, Univ. Montpellier 2, Montpellier
  • fYear
    2008
  • fDate
    3-5 Dec. 2008
  • Firstpage
    415
  • Lastpage
    420
  • Abstract
    Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, the scope of this paper is to evaluate, on and for FPGA, the robustness of triple rail logic against power analyses. More precisely, this paper aims at demonstrating that the basic concepts on which leans this logic are valid and may provide interesting design guidelines to obtain DPA (differential power analysis) resistant circuits.
  • Keywords
    field programmable gate arrays; information retrieval; logic programming; security of data; FPGA; data secrecy retrieval; differential power analysis resistant circuits; power analyses; side channel attacks; triple rail logic robustness; Cryptography; Encoding; Energy consumption; Field programmable gate arrays; Logic circuits; Logic design; Rails; Reconfigurable logic; Robustness; Timing; CPA; DPA; SCA; STTL;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4244-3748-1
  • Electronic_ISBN
    978-0-7695-3474-9
  • Type

    conf

  • DOI
    10.1109/ReConFig.2008.75
  • Filename
    4731830
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2102208