High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms

This is the first implementation in FPGA of the recently published class of public key algorithms - MQQ, that are based on quasigroup string transformations. Our implementation achieves decryption throughput of 399 Mbps on an Xilinx Virtex-5 FPGA that is running on 249.4 MHz. The encryption throughput of our implementation achieves 44.27 Gbps on an Xilinx Virtex-5 chip that is running on 276.7 MHz. Compared to RSA implementation on the same FPGA platform this implementation of MQQ is 10,000 times faster in decryption, and is more than 17,000 times faster in encryption. The main goal of this work was to build a hardware that can perform operations with the public and the private key that have as high as possible speed. Our main comparison is with RSA with a similar cryptographic strength, because we want to emphasize that RSA being essentially sequential algorithm can not benefit from the parallel capabilities that modern FPGAs offer, while MQQ can.