DocumentCode
2102282
Title
High performance median FPGA implementation for machine vision applications
Author
Sotiropoulou, C.-L. ; Gentsos, Christos ; Nikolaidis, S.
Author_Institution
Dept. of Phys., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
fYear
2013
fDate
8-11 Dec. 2013
Firstpage
173
Lastpage
176
Abstract
This paper presents a high performance median implementation targeting detection of microfluidic flows on Lab-on-Chips on a real-time machine vision implementation. We propose and implement a novel architecture which calculates the 2D median coordinates of a set of “active pixels” in a detection window of generic size. The proposed implementation takes full advantage of the FPGA´s characteristics to achieve full performance and is part of a machine vision system which achieves real-time microfluidic flow detection on 1Mpixel input videos at 60fps. The median module itself is flexible and generic and can be used for numerous machine vision applications achieving a median calculation in a very small number of clock cycles with an operational frequency of 204MHz.
Keywords
computer vision; field programmable gate arrays; lab-on-a-chip; microfluidics; object detection; video signal processing; 1Mpixel input videos; 2D median coordinates; active pixels; clock cycles; detection window; high performance median FPGA implementation; lab-on-chips; machine vision applications; microfluidic flow detection; real-time machine vision implementation; Clocks; Field programmable gate arrays; Machine vision; Microfluidics; Radiation detectors; Real-time systems; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location
Abu Dhabi
Type
conf
DOI
10.1109/ICECS.2013.6815382
Filename
6815382
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