DocumentCode
2102467
Title
Stack based module generator for analog MOS circuits
Author
Spânoche, Sorin-Andrei ; Arsintescu, George Bogdan
Author_Institution
Politehnica Univ. of Bucharest, Romania
Volume
1
fYear
1996
fDate
9-12 Oct 1996
Firstpage
139
Abstract
This paper describes a novel method for analog circuit partitioning and MOS transistor stacking. The method is based on a new algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database and transistor size trimming. Experimental results show the effectiveness of the method that is described
Keywords
MOS analogue integrated circuits; integrated circuit layout; modules; MOS transistor stacking; algorithm; analog MOS circuit; circuit partitioning; heuristics; pattern database; stack based module generator; transistor size trimming; Cost function; Databases; Integrated circuit interconnections; Manuals; NP-complete problem; Parasitic capacitance; Partitioning algorithms; Shape; Simulated annealing; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 1996., International
Conference_Location
Sinaia
Print_ISBN
0-7803-3223-7
Type
conf
DOI
10.1109/SMICND.1996.557324
Filename
557324
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