Single-electron-transistor behavior in deep sub-0.1 μm planar-doped-barrier FETs

Planar-doped-barrier FETs (PDBFETs) show low-temperature current measurements similar to those of single-electron-transistors (SETs). Also, it appears from simulation that a dynamic LDD-like region in the PDBFET is created when the device is under gate bias. This paper discusses the concept of an N-PDBFET working as a SET. Under no gate bias, the silicon band-gap forms a large barrier which prevents tunneling from occurring. In addition, the region underneath the valence band can be treated as a quasi-continuum. However, under gate bias, the barrier produced by the silicon band-gap is narrowed significantly and discrete energy levels begin to appear under the valence energy band, enabling electrons to tunnel through the available valence energy states. Similarly, in P-PDBFETs, hole tunneling through available conductance energy states occurs.