A novel fast parallel signed-digit hybrid multiplication scheme for digital systems

The performance of any digital system largely depends on the speed of data processing, especially on the performance of the multiplier in its floating-point unit. In this paper, a new radix-16 multiplication scheme that includes a new carry-free parallel adder and a novel parallel-conversion method has been proposed. The latency of processing data in any multiplier largely depends on the delay of generating multiples, the delay of adding partial products and the delay of final full-addition or conversion. These new adder and converter utilize bit by bit parallelism without any carry propagation. Therefore, this totally parallel multiplier will play an important role in the reduction of latency and also in enhancing the throughput for digital systems. The proposed system provides at least a 25% speed improvement without significantly increasing the cost