Hardware Implement of the Forward Value Conversion Algorithm for Delta-Sigma System Based Direct Stream Digital

Because the parallel data processing and the fast carry-free algorithm can be achieved by using residue number system (RNS) in VLSI (very large scale integration) design, RNS (residue number system) shows the high performance, such as low power consumption, small area, and short delay, etc. This paper presents the bit stream to RNS converting procedure based on (2ⁿ-1)2ⁿ (2ⁿ+1) moduli set. The converting circuit is designed by using Verilog language. The converter in this paper converts directly the bit stream to RNS form, having better application features for delta-sigma system based on DSD (direct stream digital). As result, the whole circuit logic is simplified and the circuit characteristic is improved.