Title :
Strained SOI technology for high-performance, low-power CMOS applications
Author :
Takagi, S.-I. ; Mizuno, T. ; Tezuka, T. ; Sugiyama, N. ; Numata, T. ; Usuda, K. ; Moriyama, Y. ; Nakaharai, S. ; Koga, J. ; Tanabe, A. ; Maeda, T.
Author_Institution :
MIRAI-ASET, Kawasaki, Japan
Abstract :
Advantages of strained-SOI CMOS and the impact on circuit performance are presented from the viewpoint of ring oscillator speed, floating body effects, threshold voltage control and gate leakage reduction. Circuit performance enhancement of about 1.7 times over conventional SOI CMOS is verified experimentally at 0.95/spl mu/m gate lengths and theoretically expected even at gate lengths of 50nm.
Keywords :
CMOS integrated circuits; low-power electronics; silicon-on-insulator; 0.95 micron; 50 nm; floating body effect; gate leakage current; low-power CMOS circuit; ring oscillator; strained SOI technology; threshold voltage; CMOS technology; Charge carrier processes; Circuit optimization; Electron mobility; Germanium silicon alloys; MOSFET circuits; Ring oscillators; Semiconductor device modeling; Silicon germanium; Silicon on insulator technology;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234343
