A hardware multiplier design of embedded microprocessor

This paper designs and realizes a hardware multiplier module, compatible with signed/unsigned 32-bit data. It adopts Radix-8 Booth algorithm to reduce the number of partial products, and proposes a method called high-position accumulation to compress them, with small area and circuit delay. We implement three various multipliers single-cycle, pipeline and multi-cycle, which could be effectively configured according to the specific features of embedded microprocessor. This paper describes our designs with Verilog HDL and utilizes Quartus II 7.2 software of Alteral firm to analyse and synthesize them, simultaneously presents a scheme of simulation and verification. The experiment result indicates that our designs possess a high performance-price ratio on the area and rate target.