An 800MHz star-connected on-chip network for application to systems on a chip

Author

Se-Joong Lee ; Seong-Jun Song ; Kangmin Lee ; Jeong-Ho Woo ; Sung-Eun Kim ; Byeong-Gyu Nam ; Hoi-Jun Yoo

Author_Institution

KAIST, Daejeon, South Korea

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

468

Abstract

A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network. The chip consists of a PLL, 1KB SRAM, two 2/spl times/2 crossbar switches, Up/Down-Samplers, two off-chip gateways, and synchronizers. The on-chip network contains 81k transistors, dissipates 264mW at 2.3V and 800MHz, and provides 1.6GB/s per port and 12.8GB/s aggregated bandwidth, supporting plesiochronous communication without global synchronization.

Keywords

SRAM chips; integrated circuit interconnections; phase locked loops; synchronisation; system-on-chip; 1 KB; 1.6 GB/s; 12.8 GB/s; 2.3 V; 264 mW; 800 MHz; PLL; SRAM; aggregated bandwidth; crossbar switches; off-chip gateways; plesiochronous communication; star-connected on-chip network; synchronizers; systems on a chip; up/down-samplers; Clocks; Frequency synchronization; Integrated circuit interconnections; Logic; Master-slave; Network-on-a-chip; Packet switching; Routing; Switches; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234390

Filename

1234390