DocumentCode
2108781
Title
A variable-kernel flash-convolution image filtering processor
Author
Ito, K. ; Ogawa, M. ; Shibata, T.
Author_Institution
Dept. of Frontier Informatics, Univ. of Tokyo, Japan
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
470
Abstract
A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.
Keywords
CMOS digital integrated circuits; VLSI; digital signal processing chips; image processing equipment; 0.18 micron; 1.8 V; 50 MHz; CMOS 5M technology; VLSI; image filtering processor; quaternary-tile pixel-data mapping; single-clock-cycle kernel convolution; variable data masking techniques; Convolution; Decoding; Filtering algorithms; Image processing; Image recognition; Indium tin oxide; Informatics; Kernel; Pixel; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234391
Filename
1234391
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