The novel arithmetic and realization based on FPGA module design for the real time compensation of the reset error in FOG

In order to reduce the size of the processing circuit, and realize the real time compensation of the reset error in fiber optic gyro (FOG). A new arithmetic and realization base on field programmable gate array (FPGA) is presented in this paper. At first the reset error and the insufficiency of usual compensation scheme are analyzed. Then a novel arithmetic which based on binary algebraic operation is described. And the functional design of arithmetic implementation was completed by using modular design method. Thus the embedded module substitutes part of the processing circuit, and the small volume, light weight, low power consumption are achieved. At last the function of the module was tested, and the result indicates that the arithmetic and implementation are valid and available.