Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC)

This paper investigates the viability of using leakage power consumption as a source of side channel information. The side channel effect is characterized in leakage power. It is shown that the increasing trend of leakage power is highly correlated with security vulnerability of cryptosystems. Addressing the severity of the side channel threat in nanoscale Cryptosystem-on-Chip (CoC), we examine the leakage reduction techniques for the side channel security application. The result shows among the circuit-based reduction techniques high V_th transistor assignment which significantly reduces both average and standard deviation of the leakage power can be exploited as a side channel aware leakage reduction in design and implementation of CoC in submicron era. The findings in this work which are presented for the first time are crucial for the development of side channel resistant cryptosystems in the upcoming CMOS technologies.