Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication

Reducing off-chip bus power consumption has become one of the key issues for low power system design. Although methods have been proposed to reduce the power dissipated in parallel buses, these techniques do not apply to serial communication since they work on consecutive data words. The data line in synchronous serial communication is a major source of power dissipation, apart from the clock line. The clock line cannot be modified due to the requirements of data recovery. This work outlines a novel transition inversion based data coding protocol by which these transitions on the data line can be reduced for synchronous serial buses like JTAG, SPI, I2C etc. Simulation results show up to 31.9% reduction in transitions, with negligible performance loss. Analysis on the utility of the proposed technique for error detection shows that the technique can be used instead of the parity bit technique since both are found to have the same average error detection capability.