Title :
VLSI architecture for digital-recurrence algorithms on divider
Author :
Yang, Jing-ling ; Choy, Chiu-Sing ; Chan, Cheung-Fat
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Abstract :
The digital-recurrence algorithms based on redundant quotient-digit set and prediction of result-digits have significant speed and cost advantages. Here we propose a VLSI implementation architecture which uses a register free domino structure to reduce the number of gates, as well as to make the circuit work at high speed. The results circuit in 0.6 μm CMOS technology has a area of 1.8 mm×1.9 mm and the evaluation time for 8-bit quotient-digit generation is about 13 ns
Keywords :
CMOS logic circuits; VLSI; dividing circuits; redundant number systems; 0.6 mum; 8 bit; CMOS technology; VLSI architecture; cost advantage; digital recurrence algorithms; divider; evaluation time; high speed circuit; quotient-digit generation; redundant quotient-digit set; register free domino structure; result-digits prediction; speed advantage; Adders; Algorithm design and analysis; Analytical models; Approximation algorithms; Approximation methods; CMOS technology; Circuits; Costs; Registers; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-5957-7
DOI :
10.1109/CCECE.2000.849739
