Consideration to minimize power losses in synchronous rectification

A synchronous rectification in high performance converter design is an essential block for low voltage and high current applications since significant efficiency and power density improvements can be achieved by replacing Schottky rectification with synchronous rectification MOSFETs. Many critical parameters for synchronous rectification MOSFETs and even parasitic components in devices and printed circuit board directly affect to system efficiency of synchronous rectifications. Optimization of the MOSFETs plays an important role in improving efficiency of synchronous rectification. This paper shows the impact of power MOSFET parameters and parasitic inductance on efficiency of synchronous rectification through loss analysis of power MOSFET from an experiment and a simulation results.