• DocumentCode
    2115479
  • Title

    Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging

  • Author

    Dudek, Rainer ; Walter, Hans ; Doering, Ralf ; Michel, Bernd ; Meyer, Thorsten ; Zapf, Joerg ; Hedler, Harry

  • Author_Institution
    Fraunhofer IZM, Micro Mater. Center Berlin & Chemnitz
  • fYear
    2006
  • fDate
    24-26 April 2006
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased reliability on module level with advantages in processing and the capability of full wafer level test and burn-in is ELASTecreg (ELASTec hArr Elastic-bump on Silicon Technology), particularly developed for memory products. The new failure risks are mainly related to fatigue of the metallic redistribution layer (RDL). Parametric studies using finite element analyses (FEA) were performed to avoid excessive straining of the metal lines. A balance of metal straining and solder straining had to be achieved. Comparisons were made for different soft bump layouts and RDL patterns. Optimal solutions figured out by FEA were also investigated experimentally by thermal cycle tests. However, the thermo-mechanical characteristics like stress-strain behaviour and fatigue resistance of the metallic films are the most important parameters for reliability predictions. In particular, the elastic-plastic properties of thin metallic Cu and Ni films are shown to depend on features like film thickness, grain size and orientation, resulting in a thin film strength exceeding the bulk strength of the same metal by several hundred percent
  • Keywords
    finite element analysis; integrated circuit packaging; solders; thermal management (packaging); thermomechanical treatment; ELASTec; fatigue resistance; finite element analysis; full wafer level test; grain size; metallic redistribution layer; resilient contact systems; solder balls; solder straining; stress-strain behavior; thermal cycle tests; thermal cycling; thermomechanical design; thermomechanical reliability; thin film strength; wafer level packaging; Costs; Fatigue; Finite element methods; Packaging; Parametric study; Performance analysis; Silicon; Testing; Thermomechanical processes; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006. EuroSime 2006. 7th International Conference on
  • Conference_Location
    Como
  • Print_ISBN
    1-4244-0275-1
  • Type

    conf

  • DOI
    10.1109/ESIME.2006.1644012
  • Filename
    1644012