Title :
Optimization on instruction reorganization
Author :
Lai, Feipei ; Lee, Hung-Chang ; Lee, Chun-Luh
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Because of the overlapped execution of instructions, the result of an instruction may be used before it is available. One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by T. Gross (1983) and J. Hennessy and T. Gross (1983) had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm does better at the same cost
Keywords :
instruction sets; pipeline processing; conflict condition; instruction reorganization; overlapped execution; partitioning; performance; pipelined processor; Circuits; Computer science; Cost function; Hardware; Heuristic algorithms; Parallel processing; Pipelines; Processor scheduling; Registers; Scheduling algorithm;
Conference_Titel :
Microprogramming and Microarchitecture. Micro 23. Proceedings of the 23rd Annual Workshop and Symposium., Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-2124-9
DOI :
10.1109/MICRO.1990.151436
