Design of a half-toning integrated circuit based on analog quadratic minimization by non linear multistage switched capacitor network

As part of an effort to build a smart sensor, the authors present the design of a neural network performing the minimization of a quadratic distance between the analog acquired picture and a convolution of the resulting halftoned binary picture. It is shown that using a diffusion kernel and switched-capacitor networks results in an effective halftoning circuit, well-suited to a very compact CMOS implementation. It is concluded that this design methodology can be utilized for the implementation of a large class of early or low-level vision problems, expressed as quadratic cost function minimization