Study on the FPGA implementation algorithm of effictive FIR filter based on remainder theorem

To minimize the logic resources and improve the operation speed, a new kind of FPGA implementation algorithm of distributed arithmetic FIR filter is presented, which is based on remainder theorem. In this algorithm, firstly the input signal and FIR filter´s coefficients are respectively transformed into remainder number, then the filtering operation are carried out by MAC module with folding structure and pipeline organization, finally the remainder number of MAC result are transformed into binary data. The ModelSim simulation result shows that the implementation method is feasibly and effictive and comparing with the traditional methods can enormously reduce the logic resources.