Widening of FUSI RTP Process Window by Spike Anneal

Author

Lauwers, A. ; Mertens, S. ; Absil, P. ; Chiarella, T. ; Hoffmann, T. ; Kubicek, S. ; De Marneffe, J.F. ; Brijs, B. ; Vrancken, C. ; Biesemans, S. ; Kittl, J. ; Verheyden, K. ; Vanormelingen, K. ; Granneman, E.

Author_Institution

IMEC, Leuven

fYear

2007

fDate

2-5 Oct. 2007

Firstpage

111

Lastpage

117

Abstract

The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni₃Si₂ at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW < 50degC) compared to soak anneals (15degC < PW < 25degC). Good overlap between the RTP1 process window for nMOS (NiSi or Ni₃Si₂ at the FUSI/dielectric interface) and the RTP1 process window for pMOS (Ni-rich silicide at the interface) is achieved by the reduction of the poly-Si height for the pMOS gate.

Keywords

MOS integrated circuits; nickel alloys; rapid thermal annealing; silicon alloys; NiSi; NiSi - Interface; blanket wafers; dielectric interface; fully silicided RTP process; nMOS; pMOS gate; spike anneal; temperature process window; Annealing; Dielectric devices; Dielectric measurements; Electric variables measurement; MOS devices; Scanning electron microscopy; Silicidation; Silicides; Temperature distribution; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on

Conference_Location

Catania, Sicily

Print_ISBN

978-1-4244-1228-0

Electronic_ISBN

978-1-4244-1228-0

Type

conf

DOI

10.1109/RTP.2007.4383828

Filename

4383828