Study on Cu Protrusion of Through-Silicon Via

The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC) packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely known challenges is via protrusion. Annealing a TSV wafer puts the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is forced out of the blind TSV. This phenomenon occurs because the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) surrounding it. Cu protrusion can lead to crack or delamination of the back-end-of-line, thus, it is a risky threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscopes and atomic force microscopes are used to observe the protrusion shape and measure the height. An electron backscatter diffraction technique is implemented to study the grain size distribution and evolution inside Cu vias. For the experiment, arrays of 5-μm TSVs are fabricated and annealed in nitrogen gas environment in different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then carried out. Based on the verified FEA methodology, several parametric studies are then conducted, including the effect of via diameter, depth, pitch, annealing temperature, and duration on Cu protrusion and TSV stress. The simulation results help to understand and solve the key problem in TSV fabrication process and reliability challenge.