AREAL: automated reasoning expert for analogue layout

Author

Ahmad, H.H. ; Mack, R.J.

Author_Institution

Centre for VLSI Syst. Design, Essex Univ., Colchester, UK

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

659

Abstract

A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution

Keywords

Boolean functions; analogue circuits; circuit layout CAD; expert systems; integrated circuit technology; linear integrated circuits; network topology; spatial reasoning; AREAL; Boolean relations; Boolean-constraint-solver; CAD; analogue circuit layout generation; automated reasoning expert for analogue layout; connectivity information; controlled branch-and-bound process; geometric constraints; geometric reasoning; knowledge; optimal solution; topological constraints; Circuit optimization; Constraint optimization; Control systems; Cost function; Optimal control; Process control; Routing; Silicon; Space exploration; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326803

Filename

326803