Title :
Efficient calculation of Boolean relations for multi-level logic optimization
Author :
Wurth, Bernd ; Wehn, Norbert
Author_Institution :
Inst. of Electron. Design Autom., Tech. Univ. Munich, Germany
fDate :
28 Feb-3 Mar 1994
Abstract :
A new exact technique is presented to calculate the maximal Boolean relation for an arbitrary subcircuit in a multi-level logic circuit. The new technique significantly reduces the memory required for BDD-based Boolean relation calculation. It therefore permits the calculation of Boolean relations for much more complex circuits than was previously possible. The efficiency of the technique is demonstrated on various benchmark circuits. An application to multi-level logic optimization is shown
Keywords :
Boolean functions; logic design; many-valued logics; BDD-based calculation; Boolean relations; binary decision diagram; multilevel logic optimization; Boolean functions; Circuit synthesis; Data structures; Design optimization; Electronic design automation and methodology; Flexible printed circuits; Logic circuits; Logic design; Microelectronics; Wire;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326812
