Title :
Data compression for thermal mitigation in the Hybrid Memory Cube
Author :
Khurshid, Mushfique Junayed ; Lipasti, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
Abstract :
Main memory performance is becoming an increasingly important factor contributing to overall system performance, especially due to the so-called memory wall. The Hybrid Memory Cube (HMC) is an attempt to overcome this memory wall by stacking DRAM on top of a logic die and interconnecting them with dense and fast through silicon vias (TSVs). However, modeling the Hybrid Memory Cube in HotSpot has indicated that this cube has a natural temperature variation, with the hottest layers at the bottom and the cooler layers at the top. High temperatures and variations within a DRAM can result in reduced performance and efficiency, especially when dynamic thermal management (DTM) schemes are used to throttle DRAM bandwidth whenever temperature gets too high. Hence this paper attempts to reduce the maximum temperature and variation by using data compression, where the compression is performed in the on chip memory controller, and the compressed blocks are read/written using fewer bursts in the Hybrid Memory Cube, hence reducing power dissipation. The compressed blocks are stored only in the hotter banks of the cube to mitigate the thermal gradient in the cube. Maximum temperature was reduced by as much as 6°C, and since the HMC spent lesser time throttling when DTM schemes were used, a maximum of 14.2% speed up was observed, at an average of 2.8%.
Keywords :
DRAM chips; data compression; logic circuits; memory architecture; storage management; thermal management (packaging); three-dimensional integrated circuits; DRAM bandwidth; DRAM interconnection; DRAM stacking; DTM scheme; HMC; HotSpot; TSV; block compression; chip memory controller; data compression; dynamic thermal management; hybrid memory cube; logic die; main memory performance; memory wall; natural temperature variation; overall system performance; power dissipation reduction; thermal gradient mitigation; through silicon vias; Bandwidth; Benchmark testing; Data compression; Memory management; Random access memory; Temperature distribution; Thermal management;
Conference_Titel :
Computer Design (ICCD), 2013 IEEE 31st International Conference on
Conference_Location :
Asheville, NC
DOI :
10.1109/ICCD.2013.6657041