Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits

Power is increasingly the primary design constraint for chip designers and one of the main techniques for addressing this concern is aggressive voltage scaling. Device variability increases with voltage scaling and significantly affects gate delays at low voltages. Although existing delay models for near- and sub-threshold circuits capture the effects of variability on gate delays, they do not capture advanced delay phenomenon such as multiple input switching (MIS; also known as near-simultaneous transitions) at inputs of a gate. As a result, most of these gate delay models often grossly underestimate worst case delays, leading to selection of non-critical paths and generation of delay-inferior vectors for post-silicon timing related tasks. In this paper we present extensive experimental results to demonstrate that MIS has significant impact (around 30-40%) on delays of near-and sub-threshold nominal gates. We develop our model which guarantees that the minimum and maximum delay values it computes are guaranteed to bound the corresponding delay values in silicon. We show that our model has practical run-time complexity and works equally well for super-, near- and sub-threshold circuits. In particular, via extensive experimentations we show that our model never underestimates the delay and tightly bounds the actual delays. We also illustrate trade-offs between tightness of such bounds, their impact on validation cost, and runtime complexity.