DocumentCode :
2124532
Title :
Optimization of address generator hardware
Author :
Grant, D.M. ; van Meerbergen, J. ; Lippens, P.E.R.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fYear :
1994
fDate :
28 Feb-3 Mar 1994
Firstpage :
325
Lastpage :
329
Abstract :
This paper describes an optimization process specific to address generation hardware. By examining a set of pre-defined address sequences at both the word- and bit-levels, a pool of possible hardware solutions may be created from which a global, optimal, bit-level implementation must be found which covers all address sequences. Optimization is completed following a generally iterative method and the resulting architecture may be further improved using generic logic synthesis. The whole process has been implemented in the tool ZIPPO and results for industrially relevant examples are presented
Keywords :
iterative methods; logic CAD; ZIPPO; address generator hardware; bit-level implementation; generic logic synthesis; iterative method; optimization process; pre-defined address sequences; target architecture; word-levels; Algorithm design and analysis; Counting circuits; Design optimization; Electrical capacitance tomography; Hardware; Industrial control; Iterative methods; Logic design; Optimization methods; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
Type :
conf
DOI :
10.1109/EDTC.1994.326857
Filename :
326857
Link To Document :
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