Synthesis of sequential machines with reduced testing cost

Author

Wang, Sying-Jyan

Author_Institution

Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

302

Lastpage

306

Abstract

We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines

Keywords

design for testability; finite state machines; graph theory; logic design; logic testing; sequential circuits; sequential machines; FSM STG; finite state machine; sequential machines; state transition graph; synthesis procedure; testable sequential machines; testing cost reduction; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Controllability; Costs; Hardware; Observability; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326860

Filename

326860