DocumentCode
2125491
Title
Demonstration of 5T SRAM and 6T dual-port RAM cell arrays
Author
Tran, H.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1996
fDate
13-15 June 1996
Firstpage
68
Lastpage
69
Abstract
This paper describes new circuit techniques that provide robust operations for a five transistor, single bitline SRAM cell design. The techniques have been implemented in an array of six transistor memory cells and operated as a dual-port RAM. The array has been fabricated using 0.6 /spl mu/m CMOS technology, and the test results show the array is capable of operating as a dual-port memory over a wide voltage supply range.
Keywords
CMOS memory circuits; SRAM chips; cellular arrays; 0.6 micron; 5T cell; 6T cell; CMOS technology; dual-port RAM cell arrays; five transistor memory cells; single bitline SRAM cell design; six transistor memory cells; CMOS technology; Circuit testing; Random access memory; Read-write memory; Robustness; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507719
Filename
507719
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