Title :
Logic synthesis and verification of the CPU and caches of a mainframe system
Author :
Nguyen, H.N. ; Tual, J.P. ; Ducousso, L. ; Thill, M. ; Vallet, P.
Author_Institution :
Dept. of Design Methodology, BULL SA, Les Clayes-sous-Bois, France
fDate :
28 Feb-3 Mar 1994
Abstract :
This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits
Keywords :
buffer storage; circuit CAD; formal verification; logic CAD; mainframes; BONSAI system; CPU design; cache design; formal verification; logic synthesis; mainframe system; Application software; CMOS logic circuits; Central Processing Unit; Circuit synthesis; Design methodology; Hardware; Logic circuits; Logic design; Signal synthesis; Timing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326898
