Title :
A suggestion for accelerating the analog fault simulation
Author :
Vermeiren, Wolfgang ; Straube, Bernd ; Elst, Günter
Author_Institution :
Fraunhofer-Inst. fur Integrierte Schaltungen, Erlangen, Germany
fDate :
28 Feb-3 Mar 1994
Abstract :
On the assumption that a commercial analog simulation tool is used an accelerated analog fault simulation can be carried out by simultaneous simulations of several faulty networks using external user written programs. If clusters with faults having similar sensitivity and temporal effects to the output can be constructed and when the faults of each cluster are simulated simultaneously a further speed-up can be achieved
Keywords :
analogue circuits; circuit analysis computing; fault location; SABER; accelerated analog fault simulation; clusters; external user written programs; faulty networks; hyper-networks; sensitivity; simultaneous simulations; speed-up; temporal effects; Acceleration; Analytical models; Circuit faults; Circuit simulation; Computational modeling; Digital circuits; Electrical fault detection; Fault detection; Signal design; Virtual manufacturing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326961
